;********************************************************************** ; * ; Three channel relay controller with with preset overlap / deadband * ; delay on switchover * ; * ;********************************************************************** ; Filename: ctrlswitch100.asm * ; Date: 03-12-2011 * ; File Version: 1.0.0 * ; * ; Author: Pete Griffiths * ; Company: Picprojects * ; * ;********************************************************************** ; * ; Files Required: P12F629.INC * ; * ;********************************************************************** ; * ; Notes: * ; * ; * ; Fit pull up resistors between Vdd and input ports * ; Inputs are active low (switch to ground) * ; * ; Outputs are active high * ; * ; Pin 1 Power Vdd +5 volts * ; Pin 2 (GPIO5) digital input - Channel 1 switch * ; Pin 3 (GPIO4) digital input - Channel 2 switch * ; Pin 4 (GPIO3) digital input - Channel 3 switch * ; Pin 5 (GPIO2) digital output - Channel 3 output * ; Pin 6 (GPIO1) digital output - Channel 2 output * ; Pin 7 (GPIO0) digital output - Channel 1 output * ; Pin 8 Power Vss * ; * ; * ;********************************************************************** list p=12F629 ; list directive to define processor #include ; processor specific variable definitions __CONFIG _CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _INTRC_OSC_NOCLKOUT & _MCLRE_OFF & _CPD_OFF errorlevel -302 ; suppress message 302 from list file ;***** VARIABLE DEFINITIONS cblock 0x20 V.w_temp ; variable used for interrupt context saving V.status_temp ; variable used for interrupt context saving V.flag.bits ; variable for flag bits V.tick ; TMR0 interrupt tick count V.state ; state variable for switch over code functions V.output ; working copy of output port V.switch.number V.switches V.switches.temp C.switching.delay V.switching.timer V.switch.mode ; C.debounce.delay V.debounce.timer V.limit.l V.limit.m endc ;***** GPIO port bits PB.ch1.switch equ .5 ; Ch1 switch input PB.ch2.switch equ .4 ; Ch2 switch input PB.ch3.switch equ .3 ; Ch3 switch input PB.ch1.out equ .0 ; Ch1 control output PB.ch2.out equ .1 ; Ch2 control output PB.ch3.out equ .2 ; Ch3 control output ;***** flag bits (in flag.bits variable F.tick equ .0 ;********************************************************************** ORG 0x000 ; processor reset vector goto main ; go to beginning of program ;********************************************************************** ; Interrupt handler ORG 0x004 ; interrupt vector location int.main movwf V.w_temp ; save off current W register contents movf STATUS,w ; move status register into W register movwf V.status_temp ; save off contents of STATUS register banksel INTCON int.timer0 bcf INTCON,T0IF ; clear TMR0 interrupt flag call check.switches movf V.switch.mode,F ; test v.switch.mode skpnz ; skip next if was not zero call overlap.state.switcher ; else run overlap state function movf V.switch.mode,F ; test v.switch.mode skpz ; skip next if it was zero call deadband.state.switcher ; else run deadband state function ; Tick base timer: ; 1uS clock ; 1:2 prescaler ; .0000001 x (2*256) = 512uS (0.512mS) bsf V.flag.bits, F.tick ; set the tick flag int.exit movf V.status_temp,w ; retrieve copy of STATUS register movwf STATUS ; restore pre-isr STATUS register contents swapf V.w_temp,f swapf V.w_temp,w ; restore pre-isr W register contents retfie ; return from interrupt ;********************************************************************** main ; start of code initialization clrf GPIO banksel CMCON movlw 1< output overlap delay ; 1 -> output deadband delay de .0 ;---------------------------- ; address 0x02 ; debounce timer x 0.512mS de .40 ;---------------------------- ORG 0x2110 dt "V1.00, " dt "Relay Channel Switch Controller. " dt "Picprojects (c) 2011, " dt "Pete Griffiths " END ; directive 'end of program'